S. Ikenaga

The impact of data-line interference noise on DRAM scaling

Y. Nakagome, Masakazu Aoki, S. Ikenaga et al. · IEEE Journal of Solid-State Circuits · 1988 · 71 citations

Cell Array Architecture, Dynamic Behavior, Engineering +11

An experimental large-capacity semiconductor file memory using 16-levels/cell storage

Masashi Horiguchi, Masahiro Aoki, Y. Nakagome et al. · IEEE Journal of Solid-State Circuits · 1988 · 42 citations

Non-volatile Memory, Engineering, Memory Design +17

A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure

Masakazu Aoki, Y. Nakagome, Masashi Horiguchi et al. · IEEE Journal of Solid-State Circuits · 1988 · 36 citations

Engineering, Vlsi Design, High Bandwidth Memory +14

A 16-level/cell dynamic memory

Masahiro Aoki, Y. Nakagome, Masashi Horiguchi et al. · IEEE Journal of Solid-State Circuits · 1987 · 30 citations

Storage Levels, Electrical Engineering, Non-volatile Memory +13

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier

Masashi Horiguchi, Masashi Aoki, J. Etoh et al. · IEEE Journal of Solid-State Circuits · 1990 · 29 citations

Low-power Electronics, Electrical Engineering, Cmos-dram Voltage Limiter +9