IEEE Transactions on Electron Devices · 1987 · 51 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignBipolar Junction TransistorsCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyHigh-frequency Semiconductor DevicesIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsBicmos TechnologyCmos Fabrication ProcessesCmos OscillatorsCutoff FrequencyHigh-speed Cmos DesignLatchup MitigationPolysiliconSize
A buried twin well and polysilicon emitter structure is developed for high-speed BiCMOS VLSI's. A bipolar transistor of high cutoff frequency (f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> = 4 GHz) and small size (500 µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) has been fabricated on the same chip with a standard 2-µm CMOS, without degrading the device characteristics of the MOSFET. Latchup immunity is improved due to the low well resistance of the buried layer. The well triggering current is a 0.5-1.0 order of magnitude higher than that of a standard n-well CMOS. To evaluate the utility of this technology, a 15-stage ring oscillator of the 2NAND BiCMOS gate is fabricated. The gate has a 0.71-ns propagation delay time and 0.25-mW power dissipation at 0.85-pF loading capacitance and 4-MHz operation. Drive ability is 0.24 ns/pF, which is 2.5 times larger than that of the equal-area CMOS gate.
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High speed BiCMOS VLSI technology with buried twin well structure
Atsuo Watanabe, Takahide Ikeda, T. Nagano et al. · 1985 · 25 citations
Engineering, Computer Engineering, Electrical Engineering +15
A merged CMOS/bipolar VLSI process
F.W. Walczyk, J. Rubinstein · 1983 · 21 citations
Engineering, Computer Engineering, Electrical Engineering +15