M. Odaka

High-speed BiCMOS technology with a buried twin well structure

Takahide Ikeda, Atsuo Watanabe, Yoshifumi Nishio et al. · IEEE Transactions on Electron Devices · 1987 · 51 citations

Low-power Electronics, Buried Twin, Electrical Engineering +12

13-ns, 500-mW, 64-kbit ECL RAM using Hi-BiCMOS technology

K. Ogiue, M. Odaka, S. Miyaoka et al. · IEEE Journal of Solid-State Circuits · 1986 · 33 citations

Electrical Engineering, Memory Architecture, Engineering +9

Advanced BiCMOS technology for high speed VLSI

Takahide Ikeda, T. Nagano, N. Momma et al. · 1986 · 29 citations

Electrical Engineering, High Performance Bicmos, Engineering +13

A 512 kb/5 ns BiCMOS RAM with 1 kG/150 ps logic gate array

M. Odaka, Kaori Nakamura, Kayoko Eno et al. · 2003 · 25 citations

Electrical Engineering, Memory Architecture, Engineering +15

High speed BiCMOS VLSI technology with buried twin well structure

Atsuo Watanabe, Takahide Ikeda, T. Nagano et al. · 1985 · 25 citations

Electrical Engineering, Engineering, Vlsi Design +11