High-speed BiCMOS technology with a buried twin well structure

Takahide Ikeda, Atsuo Watanabe, Yoshifumi Nishio, +4

IEEE Transactions on Electron Devices

Low-power ElectronicsBuried TwinElectrical EngineeringPolysilicon Emitter StructureEngineering +10

13-ns, 500-mW, 64-kbit ECL RAM using Hi-BiCMOS technology

K. Ogiue, M. Odaka, S. Miyaoka, +3

IEEE Journal of Solid-State Circuits

Electrical EngineeringMemory ArchitectureEngineeringVlsi DesignHi-bicmos Technology +7

Advanced BiCMOS technology for high speed VLSI

Takahide Ikeda, T. Nagano, N. Momma, +4

Electrical EngineeringHigh Performance BicmosEngineeringVlsi DesignHigh-speed Electronics +11

A 512 kb/5 ns BiCMOS RAM with 1 kG/150 ps logic gate array

M. Odaka, Kaori Nakamura, Kayoko Eno, +5

Electrical EngineeringMemory ArchitectureEngineeringVlsi DesignMemory Design +13

High speed BiCMOS VLSI technology with buried twin well structure

Atsuo Watanabe, Takahide Ikeda, T. Nagano, +5

Electrical EngineeringEngineeringVlsi DesignStandard CmosHigh-frequency Device +9

A 13ns/500mW 64Kb ECL RAM

K. Ogiue, M. Odaka, S. Miyaoka, +4

Electrical EngineeringTwin-well 2μMVlsi DesignEngineeringCmos Transistors +10

A 1.5ns, 64kb ECL-CMOS SRAM

H. Nambu, K. Kanetani, Y. Idei, +9

Hardware SecurityElectrical EngineeringSeveral High-density 1MbEngineeringVlsi Design +8

A 7ns/350mW 64K ECL compatible RAM

S. Miyaoka, M. Odaka, K. Ogiue, +4

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignBipolar Transistor +9

A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM

Kizashi Yamaguchi, H. Nambu, K. Kanetani, +9

IEEE Journal of Solid-State Circuits

EngineeringVlsi DesignMemory DesignEmerging Memory TechnologyComputer Architecture +15

A 1.5 ns 256 kb BiCMOS SRAM with 11 k 60 ps logic gates

N. Tamba, K. Akimoto, M. Ohhayashi, +16

EngineeringVlsi DesignMemory DesignComputer ArchitectureHardware Systems +15