IEEE Journal of Solid-State Circuits · 2014 · 61 citations · 23 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesDevice ModelingHardware AccelerationLow-power Digital Circuit DesignMemory DevicesMemory Subsystem DesignPower ManagementMagnetoresistive Random-access MemoryMemory Circuit DesignMotion PredictionNon-volatile Memory DesignNonvolatile MemoryNonvolatile Memory DevicesPower Gating GranularityTemporal Granularity
A magnetic tunnel junction (MTJ)-based logic-in-memory hardware accelerator LSI with cycle-based power gating is fabricated using a 90 nm MTJ/MOS process on a 300 mm wafer fabrication line for practical-scale, fully parallel motion-vector prediction, without wasted power dissipation. The proposed nonvolatile LSI is designed by establishing an automated design environment with MTJ-based logic-circuit IPs and peripheral assistant tools, as well as a precise MTJ device model produced by the fabricated test chips. Through the measurement results of the fabricated LSI, this study shows both the impact of the power-gating technique in a fine temporal granularity utilizing the non-volatility of the MTJ device and the effectiveness of the established automated design environment for designing random logic LSI using nonvolatile logic-in-memory.
23