IBM Journal of Research and Development · 1992 · 10 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesDigital Logic DesignDynamic Power ReductionElectronics TechnologyIntegrated Circuit DesignLow-power Digital Circuit DesignBipolar Circuit DesignDelay MinimizationLogic Family DesignLogic Function ImplementationLogic Gate ImplementationLow-power Logic DesignSignal Propagation DelaySwitching Activity Reduction
The performance required for logic gate arrays by the IBM Enterprise System/9000™ (ES/9000™) family of water-cooled processors was obtained by redesigning chips that previously consisted of emitter-coupled logic (ECL) circuits. Multiple bipolar logic circuit families were implemented for the first time on a single IBM chip by using a modular cell approach. In 60% of the ECL circuits, ac coupling in ECL gates reduced the maximum operating power per ECL circuit on ES/9000 chips by 50% and decreased the signal delay per loaded gate by 30%, to 150 ps. About 10–20% of the remaining ECL circuits were replaced by differential current switches (DCS) which dissipated less power and improved the overall chip performance. Circuits to communicate between ECL and DCS circuit families and to improve DCS circuit reliability were included on the ES/9000 chips without affecting logic function density.
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Fault Diagnosis of Digital Systems
H. Y. Chang, E. G. Manning, Gernot Metze et al. · IEEE Transactions on Systems Man and Cybernetics · 1973 · 161 citations · Full text