Logic Gate Implementation

Logic Gate Implementation is a methodology in standard cell design that defines the specific arrangement and sizing of transistors and interconnections within a cell to realize a targeted logic function with optimized performance, area, and power characteristics.

1K

Publications

52K

Citations

4K

Authors

957

Institutions

Publications per year

2017–2026

344

Authors

4K

  1. EK
    Evgeny Katz

    Clarkson University, United States

    6 publications · 259 citations

    6

    h-index

  2. VD
    Vishwani D. Agrawal

    AT&T (United States), United States

    6 publications · 115 citations

    6

    h-index

  3. KM
    K. Maezawa

    Nagoya University, Japan

    6 publications · 413 citations

    6

    h-index

  4. NS
    N. Sandeep

    Malaviya National Institute of Technology Jaipur, India

    5 publications · 269 citations

    5

    h-index

  5. SK
    S. Kosaka

    Electrotechnical Institute, Poland

    5 publications · 138 citations

    5

    h-index

1–5 of 4K

Venues

  1. Sensors and Actuators B Chemical

    31 publications · 1.7K citations

    25

    h-index

  2. Chemical Communications

    ChemComm · 26 publications · 1.4K citations

    22

    h-index

  3. IEEE Journal of Solid-State Circuits

    27 publications · 899 citations

    19

    h-index

  4. Journal of the American Chemical Society

    JACS · 19 publications · 3.6K citations

    18

    h-index

  5. 16

    h-index

1–5