ESD protection for the tolerant I/O circuits using PESD implantation

ESD protection for mixed-voltage I/O using NMOS transistors stacked in a cascode configuration

Warren Anderson, D.B. Krakauer · 2002 · 69 citations

Engineering, Computer Engineering, Electrical Engineering +12

ESD protection in a 3.3 V sub-micron silicided CMOS technology

D.B. Krakauer · Journal of Electrostatics · 1993 · 34 citations

Engineering, Electrical Engineering, Electronic Materials +11

Grounded-gate nMOS transistor behavior under CDM ESD stress conditions

K. Verhaege, C. Russ, J.M. Luchies et al. · IEEE Transactions on Electron Devices · 1997 · 27 citations

Engineering, Electrical Engineering, Electronic Materials +16