Japanese Journal of Applied Physics · 2010 · 16 citations · 1 references
EngineeringMaterials EngineeringMaterials ScienceElectrochemistryElectronic MaterialsSemiconductor DevicesFabrication MaterialsHybrid FabricationIntegrated Circuit DesignIntegrated Circuit FabricationInterconnect TechnologySemiconductor Device MaterialsChemical Mechanical PlanarizationDual Damascene ProcessElectrochemical-mechanical CouplingPlanarizationPlanarization TechniquesThree-dimensional IntegrationThrough-silicon Via DesignThrough-silicon Vias
A hybrid electrochemical mechanical planarization and chemical mechanical planarization (e-CMP/CMP) was applied to the Cu dual-damascene through-silicon via (TSV) process for wafer-level three-dimensional integrated circuit (3D-IC) stacking. In this process, an electrochemically deposited Cu film was removed by e-CMP at a removal rate of 3.5 µm/min until the voltage endpoint was detected. Then, residual Cu film was polished off in the CMP mode using the same e-CMP pad. A fine Cu damascene structure was successfully fabricated with a dishing depth of less than 200 nm in a metal pad of 200×200 µm 2 area. The criterion of dishing without failure in the adhesive coat for 3D-IC stacking is discussed.
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