2011 · 13 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCmos Circuit DesignDigital Integrated Circuit DesignIntegrated Circuit DesignMicroarchitecture DesignMixed-signal IntegrationPhysical DesignCmos ScalingCritical SpeedHigh-speed Interface DesignProcess Design OptimizationRf Cmos DesignSpeedTechnology ConvergenceUltra-low-power Cmos
In this paper, we present a process/design co-optimization methodology for a full-SOC platform based on 28nm LP CMOS technology with high-k metal-gate (HK/MG) architecture. We report a CPU critical path speed enhancement by implementing a triple gate oxide scheme (so called 28LPG) on HK/MG scheme combined with 20fF/um2 MiM solution for decoupling capacitance. Beside digital speed, we developed a complete RF devices suite enabling high performance analog cells as LNA and VCOs. A 3D integration for high data rate interfaces as wide IOs has been demonstrated based on TSV (Through-Silicon-Via) architecture. Finally ultimate solution for ultra-low power and large memory size is proposed with embedded DRAM offering.