High-speed Interface Design
High-Speed Interface Design is a methodology within mixed-signal integrated circuit development that enables the efficient transmission and reception of data signals at multi-gigabit per second rates by integrating precise analog front-ends with high-bandwidth digital protocols on a single chip.
152
Publications
4.8K
Citations
857
Authors
124
Institutions
Publications per year
2017–2026
23
152
Die Stacking (3D) Microarchitecture
Bryan Black, Daniel Pantuso, Paul A. Reed et al. · 2006 · 599 citations
The ORNL 10-meter small angle X-ray scattering camera
R. W. Hendricks · Journal of Applied Crystallography · 1978 · 153 citations
Engineering, Radiology, Optics +16
1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme
Kensuke Kanda, Danardono Dwi Antono, Koichi Ishida et al. · 2003 · 136 citations
Engineering, Computer Engineering, Electrical Engineering +11
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124
Samsung (South Korea)
Seoul, South Korea
11 h-index
107 publications
2.1K citations
Rambus (United States)
Sunnyvale, United States
9 h-index
100 publications
4.1K citations
NEC (Japan)
Tokyo, Japan
5 h-index
19 publications
483 citations
Intel (United States)
Santa Clara, United States
5 h-index
39 publications
9K citations
Pohang University of Science and Technology
Pohang, South Korea
5 h-index
20 publications
526 citations
Stanford University
Stanford, United States
5 h-index
11 publications
938 citations
Texas Instruments (United States)
Dallas, United States
5 h-index
8 publications
186 citations
Xilinx (United States)
San Jose, United States
5 h-index
9 publications
258 citations
1–8 of 124
24 publications · 1.1K citations
17
h-index
7 publications · 231 citations
7
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5 publications · 75 citations
5
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3 publications · 36 citations
3
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2 publications · 27 citations
2
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1–5