Q-modules: internally clocked delay-insensitive modules

Abstract

Q-modules are internally clocked modules that can be used to satisfy delay-insensitive specifications. A single delay element is required with a one-sided bound that its value be greater than the maximum delay of the combination logic. Prototypes of components to implement Q-modules have been designed, and a design aid program, QSYN, to place instances of these components, personalize a PLA, and generate a MAGIC or CIF file for a CMOS realization, including the delay circuitry, is being developed. Testability is one of the advantages of Q-modules over clock-free delay-insensitive modules; circuitry is included in the cells for testing the logic and interconnections.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>