Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate length

Abstract

We have fabricated hybrid channel Ω-gate CMOS nanowires (NWs) with strained SiGe-channel (cSiGe) p-FETs and Si-channel n-FETs. An optimized process flow based on the Ge enrichment technique results in a +135% hole mobility enhancement at long gate lengths compared to Si. Effectiveness of cSiGe channel is also evidenced for ultra-scaled p-FET NWs (gate length L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> =15 nm) with +90% I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> current improvement.