Concepedia

Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product

I-Cheng Lin, Chih-Yao Huang, Chuan-Jane Chao, Ming‐Dou Ker

Microelectronics Reliability · 2003 · 12 citations · 3 references

Concepts

EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesSystem-on-chip DesignCmos Circuit DesignDevice ReliabilityCmos ReliabilityLatchup MitigationOn-chip Electrostatic Discharge Protection

References

3

Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI

Ming‐Dou Ker · IEEE Transactions on Electron Devices · 1999 · 311 citations

Engineering, Electrical Engineering, Microelectronics +8

Latchup in CMOS technology

M. Hargrove, Steven H. Voldman, R. Gauthier et al. · 1998 · 61 citations

Engineering, Electrical Engineering, Microelectronics +13

A practical high-latchup immunity design methodology for internal circuits in the standard cell-based CMOS/BiCMOS LSIs

T. Aoki · IEEE Transactions on Electron Devices · 1993 · 21 citations

Engineering, Electrical Engineering, Circuit Theory +12