A New and Better Method for Extracting the Parasitic Elements of On-Wafer GaN Transistors

Abstract

By biasing the AlGaN/GaN HEMTs with low DC gate forward current and floating drain, a new method for extracting parasitic resistances and parasitic inductances is introduced. The originality of the proposed method lies in the low DC gate forward current used for extracting R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> and L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> . While the classical method for extracting R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> and L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> uses a set of S-parameters measured under different large DC gate forward current, the proposed method uses a data set of S-parameters measured at a single low DC gate forward current. The excellent agreement between model and experimental data verify the validity of the proposed method.