2013 · 25 citations · 8 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDynamic Power ReductionLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignMixed-signal IntegrationAnalog Application-specific Integrated Circuit DesignAnalog-to-digital Converter DesignCmos Analog Circuit DesignCmos Analog Integrated CircuitsHigh-voltage Power SupplyPower ConsumptionPower Consumption OptimizationReference Voltage Design
A high speed successive approximation (SAR) ADC requires reference voltage buffers with high driving capability. Moreover, the power consumption of the reference buffers is usually several times larger than that of the SAR ADC itself. Three techniques are adopted to mitigate the requirement on driving capability of reference voltage buffers for SAR ADCs. A 10b 50MS/s ADC based on the proposed techniques is presented. The prototype ADC was fabricated in 40nm LP 1P7M CMOS technology. It consumes 0.47 mW at 50 MS/s from 1.1V supply voltage and achieves ENOB of 9.18-bit and figure of merit (FoM) of 16 fJ/conversion-step. The active area is 0.0114 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
8
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
Yan Zhu, Chi‐Hang Chan, U-Fat Chio et al. · IEEE Journal of Solid-State Circuits · 2010 · 713 citations
Engineering, Computer Engineering, Electrical Engineering +17