A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

TLDR

The paper presents a 1.2 V, 10‑bit, 100 MS/s reference‑free SAR ADC. The design employs a reference‑free architecture with a common‑mode charge‑recovery switching scheme and a variable self‑timed loop to reduce switching energy, improve linearity, and accelerate preamplifier reset. The prototype achieves 3 mW total power, 56.6 dB peak SNDR, and a 77 fJ/conv‑step figure of merit while operating at high speed.

Abstract

A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.