Sai‐Weng Sin - Concepedia

Author

Sai‐Weng Sin

University of Macau ORCID

Also Known As

S.-W. Sin, Sai-Weng Sin, Sai‐Weng Sin, Sin Saiweng

213

Publications

3.6K

Citations

H-Index

Concepts

All Affiliations

University of Macau Instituto Politécnico de Lisboa University of Lisbon Instituto Superior Técnico University of Pavia

About

Sai‐Weng Sin is an author at University of Macau specializing in engineering, computer engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	25	51	2.5K
2	Computer Engineering	25	50	2.4K
3	Education	3	3	57
4	Computer Science	2	2	83
5	Medicine	1	1	18

Sai‐Weng Sin

Publications

Citations

H-Index

Page 1

	Year	Citations
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS Yan Zhu, Chi‐Hang Chan, U-Fat Chio, IEEE Journal of Solid-State Circuits Low-power ElectronicsV 10-Bit 100Electrical EngineeringEngineeringData Converter	2010	700
A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting Yan Lü, Haojuan Dai, Mo Huang, IEEE Transactions on Circuits & Systems II Express Briefs Low-power ElectronicsElectrical EngineeringEnergy HarvestingEngineeringWireless Power Transmission	2016	173
A Fully Integrated Digital LDO With Coarse–Fine-Tuning and Burst-Mode Operation Mo Huang, Yan Lü, Sai‐Weng Sin, IEEE Transactions on Circuits & Systems II Express Briefs Low-power ElectronicsBurst-mode OperationElectrical EngineeringLow-voltage OperationEngineering	2016	145
An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC He-Gong Wei, Chi‐Hang Chan, U-Fat Chio, IEEE Journal of Solid-State Circuits Resistive DacEngineeringCalibrationData ConverterAnalog Design	2012	97
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration Mingqiang Guo, Jiaji Mao, Sai‐Weng Sin, IEEE Journal of Solid-State Circuits RadarMismatch Calibration Off-chipSplit Ti TopologyEngineeringSynthetic Aperture Radar	2019	77
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS Chi‐Hang Chan, Yan Zhu, U-Fat Chio, Offset CalibrationAnalog-to-digital ConverterLow OffsetData ConverterMixed-signal Integrated Circuit	2011	74
A 550-$\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS Biao Wang, Sai‐Weng Sin, U Seng‐Pan, IEEE Journal of Solid-State Circuits Electrical EngineeringEngineeringData ConverterMixed-signal Integrated CircuitAnalog Design	2019	73
A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure Chi‐Hang Chan, Yan Zhu, Sai‐Weng Sin, Sar AdcHigh DensityEngineeringData ConverterCompact Dac Structure	2012	69
Split-SAR ADCs: Improved Linearity With Power and Speed Optimization Yan Zhu, Chi‐Hang Chan, U-Fat Chio, IEEE Transactions on Very Large Scale Integration (VLSI) Systems RadarEngineeringSuccessive Approximation RegistersSynthetic Aperture RadarData Converter	2013	67
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance Liang Qi, Ankesh Jain, Dongyang Jiang, IEEE Journal of Solid-State Circuits EngineeringCt Smash DsmHigh-frequency DeviceData ConverterMixed-signal Integrated Circuit	2019	66

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