Chun-Po Huang

Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops

Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2012 · 75 citations

Engineering, Vlsi Design, Energy Efficiency +22

Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors

Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2012 · 38 citations

Electrical Engineering, Physical Design (Electronics), Engineering +11

Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits

Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu et al. · 2011 · 31 citations

Electrical Engineering, High Dispersion, Engineering +13

A Systematic Design Methodology of Asynchronous SAR ADCs

Chun-Po Huang, Jai-Ming Lin, Ya-Ting Shyu et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2015 · 29 citations

Engineering, Vlsi Design, Analog Design +18

A 10-bit 50-MS/s SAR ADC with techniques for relaxing the requirement on driving capability of reference voltage buffers

Shao-Hua Wan, Che-Hsun Kuo, Soon-Jyh Chang et al. · 2013 · 25 citations

Reference Voltage Buffers, Sar Adc, Electrical Engineering +10