Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2009 · 48 citations · 1 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureDesign AutomationDesign OptimizationIntegrated Circuit DesignLayout OptimizationMemory Subsystem DesignPhysical DesignProcessor Core DesignVery-large-scale Integration LayoutIntegrated DesignLayout TechniquesMemory ArraysMemory Co-designTechnology ScalingTemplate DesignTemplate-based DesignYield-aware Layout
The paper highlights the need for concurrent process‑design co‑development amid discontinuous patterning and device innovation, and contrasts traditional DfM shortcomings with integrated design‑technology co‑optimization used for memory arrays. It reviews how escalating layout sensitivities increase design‑rule complexity and threaten profitable scaling, and introduces process‑side work on integrated co‑optimization not covered in this study. The authors demonstrate that a simplified, template‑based layout environment extends memory‑style design‑technology co‑optimization to logic chips, yielding higher layout density, improved patterning and electrical yield, and adaptability to 32 nm with enhanced interconnect redundancy.
The time-to-market driven need to maintain concurrent process-design co-development, even in spite of discontinuous patterning, process, and device innovation is reiterated. The escalating design rule complexity resulting from increasing layout sensitivities in physical and electrical yield and the resulting risk to profitable technology scaling is reviewed. Shortcomings in traditional Design for Manufacturability (DfM) solutions are identified and contrasted to the highly successful integrated design-technology co-optimization used for SRAM and other memory arrays. The feasibility of extending memory-style design-technology co-optimization, based on a highly simplified layout environment, to logic chips is demonstrated. Layout density benefits, modeled patterning and electrical yield improvements, as well as substantially improved layout simplicity are quantified in a conventional versus template-based design comparison on a 65nm IBM PowerPC 405 microprocessor core. The adaptability of this highly regularized template-based design solution to different yield concerns and design styles is shown in the extension of this work to 32nm with an increased focus on interconnect redundancy. In closing, the work not covered in this paper, focused on the process side of the integrated process-design co-optimization, is introduced.
1
Layout impact of resolution enhancement techniques
Lars W. Liebmann · 2003 · 114 citations