Yield-aware Layout

Yield-Aware Layout is a VLSI layout methodology that belongs to the class of design-for-manufacturability techniques, distinguished by its explicit integration of yield prediction and optimization at the physical design stage to mitigate the impact of manufacturing defects and process variations.

Publications

1.3K

Citations

127

Authors

Institutions

Publications per year

2017–2026

Parents

Very-large-scale Integration Layout

Publications

ICCAD-2012 CAD contest in fuzzy pattern matching for physical verification and benchmark suite

J. Andres Torres · 2012 · 117 citations

Architecture, Computer Engineering, Computer Science +16

A yield improvement technique for IC layout using local design rules

G.A. Allan, A.J. Walton, R.J. Holwill · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1992 · 66 citations

Engineering, Computer Engineering, Electrical Engineering +15

Targeted Layout Modifications for Semiconductor Yield/Reliability Enhancement

G.A. Allan · IEEE Transactions on Semiconductor Manufacturing · 2004 · 60 citations

Engineering, Computer Engineering, Computer-aided Design +14

Efficient process-hotspot detection using range pattern matching

Hailong Yao, Soham Sinha, C. Chiang et al. · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 2006 · 53 citations

Engineering, Manufacturing Engineering, Computer-integrated Manufacturing +9

Simplify to survive: prescriptive layouts ensure profitable scaling to 32nm and beyond

Lars W. Liebmann, Larry Pileggi, Jason Hibbeler et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2009 · 48 citations

Engineering, Computer Engineering, Computer Science +17

1–5 of 54

Authors

127

GA
G.A. Allan
University of Edinburgh, United Kingdom
4 publications · 172 citations
4
h-index
CC
C. Chiang
Synopsys (United States), United States
4 publications · 153 citations
4
h-index
IK
Israel Koren
University of Massachusetts Amherst, United States
3 publications · 70 citations
3
h-index
YC
Yunlong Cai
Zhejiang University, China
3 publications · 120 citations
3
h-index
HY
Hailong Yao
Tsinghua University, China
3 publications · 120 citations
3
h-index

1–5 of 127

Institutions

1–8 of 49

Venues

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
7 publications · 151 citations
7
h-index
Microelectronics Reliability
3 publications · 63 citations
3
h-index
Medical Entomology and Zoology
2 publications · 26 citations
2
h-index
IEEE Transactions on Semiconductor Manufacturing
2 publications · 88 citations
2
h-index
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2 publications · 85 citations
2
h-index

1–5