Numerical investigation and comparison with experimental characterisation of side gate p-type junctionless silicon transistor in pinch-off state

Abstract

A side gate p-type junctionless silicon transistor is fabricated by atomic force microscopy nanolithography using a anisotropic potassium hydroxide wet etching process on low doped (105 cm−3) silicon-on-insulator wafer. The structure is a gated resistor and turns off based on a pinch-off effect principle, when essential positive gate voltage is applied and made a sufficiently large barrier in the gating region. Negative gate voltage is unable to make a significant impact on drain current to drive the device into accumulation mode. The experimental transfer characteristic is investigated and compared with the simulation result for positive gate voltage. ‘On/off’ ratio and subthreshold swing were also measured. The numerical study of the device in ‘off’ state is investigated based on the variation of majority and minority carriers’ density and recombination generation in the active region of the device, which offers more understanding of the device operation and also for previous works.