High-throughout hardware architecture of MQ arithmetic coder

Abstract

A novel byte-out architecture in MQ arithmetic coder is proposed and the new MQ-coder hardware architecture which use the novel byte-out architecture is presented, in which it can encode two CX-D pairs per cycle. The coder is described with Verilog HDL at RTL. Synthesis, fitter, assembler and timing analyzer are conducted with Quartus II 9.0. The results of timing analyzer show that the architecture can efficiently improve the throughput and clock frequency, the throughput can achieve 117.12 MCxD · s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> and the clock frequency can achieve 58.56 MHz.