Arithmetic Unit Design is a computational architecture methodology that specifies the structural and functional organization of programmable arithmetic components within a reconfigurable fabric to optimize data path efficiency, resource utilization, and parallelism in Coarse-Grained Reconfigurable Architectures.
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A Regular Layout for Parallel Adders
Brent, Kung · IEEE Transactions on Computers · 1982 · 1.1K citations
High-Speed Arithmetic in Binary Computers
O. L. Macsorley · Proceedings of the IRE · 1961 · 622 citations
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IBM (United States)
Armonk, United States
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56 publications
2.7K citations
École Normale Supérieure de Lyon
Lyon, France
15 h-index
43 publications
2.1K citations
Centre National de la Recherche Scientifique
Paris, France
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41 publications
1.8K citations
Intel (United States)
Santa Clara, United States
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31 publications
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Nanyang Technological University
Singapore, Singapore
15 h-index
36 publications
1.8K citations
Imperial College London
London, United Kingdom
13 h-index
45 publications
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Université Claude Bernard Lyon 1
Villeurbanne, France
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32 publications
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University of Wisconsin–Madison
Madison, United States
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33 publications
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- IEEE Transactions on Computers
85 publications · 5.7K citations
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- IEEE Journal of Solid-State Circuits
24 publications · 1.2K citations
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- IEEE Transactions on Circuits and Systems I Regular Papers
20 publications · 672 citations
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- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
18 publications · 783 citations
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- IBM Journal of Research and Development
14 publications · 1.1K citations
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