A twin-well CMOS process employing high-energy ion implantation

Abstract

A twin-well CMOS process has been developed using ion implantation with energies up to 1 MeV. The high-energy ion-implantation steps eliminate the need for extended processing times at high temperatures. As a consequence, this permits an increase in packing density, independent control of critical electrical parameters, and simplified processing. The resulting process includes advantages of recent developments in bulk CMOS: an n-type isolation well in a p-p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> substrate and retrograde wells. This paper discusses the processing steps involved and provides the resulting device characteristics. An interesting application of the process is also presented, which is the realization of a gate array with TTL-compatible input and output buffers.