Technology, performance, and computer-aided design of three-dimensional integrated circuits

TLDR

3D integration refers to any process by which multiple conventional device layers may be stacked and electrically interconnected. The paper presents an overview of a new monolithic 3D integration technology, discusses its process flow, technological challenges, and design implications, and outlines anticipated performance benefits. The process combines state‑of‑the‑art single‑wafer integration with high‑density inter‑wafer interconnects to reduce wire length, area, timing, and energy consumption. Performance results demonstrate that integrating circuits in three dimensions can yield measurable improvements in key metrics.

Abstract

We present an overview of a new monolithic fabrication technology known as three-dimensional integration. 3D integration refers to any process by which multiple conventional device layers may be stacked and electrically interconnected. By combining state-of-the-art single-wafer integration with a high-density inter-wafer interconnect, our 3D integration process is capable of providing improved circuit performance in terms of metrics such as wire length, area, timing, and energy consumption. In this paper, we will discuss the overall 3D integration process flow, as well as specific technological challenges and the issues they present to circuit designers. We will also describe how these issues may be tackled during the placement, routing, and layout stages of physical design. Finally, we will present some performance results that may be obtained by integrating circuits in three dimensions.