Planar fully ion implanted InP power junction FET's

J. B. Boos, S.C. Binari, G. Kelner, Philip E. Thompson, Tianqi Weng, N. A. Papanicolaou, R.L. Henry

IEEE Electron Device Letters · 1984 · 25 citations · 6 references

Concepts

Abstract

This letter reports on the fabrication and performance of planar all ion-implanted 1.0-µm gate length InP power junction field effect transistors (JFET's). The devices were fabricated utilizing n+ implantation, a AuZn/TiW/Au gate metallization, and an n+ drain ledge. At 4.5 GHz, the 300-µm gate width JFET's exhibited maximum insertion gains of up to 13 dB and scaled output powers as high as 1 W/mm with 3-dB gain.

References

6