Investigation of low-temperature deposition high-uniformity coverage Parylene-HT as a dielectric layer for 3D interconnection

Abstract

Polymer low-k materials have been considered in literature to meet the requirements of lowering the dielectric constant of the dielectric layer to decrease the problem of signal delay, lower power consumption, and reduce cross-talk between the neighboring paths, as well as, lower the fabrication temperature budget. In this paper, the feasibility of using Parylene-HT as a low-temperature deposition intelever dielectric in 3D interconnection is investigated and the results are presented. In particular, the diffusivities of Cu in room temperature deposited high-uniformity coverage Parylene-HT at 250 ºC and 350 ºC are evaluated to be 5.7E-18 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /s and 1.3E-16 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /s respectively, by dynamic secondary ion mass spectrometry (D-SIMS) technique. In addition, the capability of embedding Parylene-HT in through-Si-via (TSV) fabrication process through the demonstration of 36-μm-diameter 100-μm-depth copper-filled TSVs using Parylene-HT as a liner, are reported.