Selective Electroless Metal Deposition for Via Hole Filling in VLSI Multilevel Interconnection Structures

Abstract

Selective electroless metal deposition process is investigated for via hole filling to provide a planar surface for the fabrication of high density multilevel interconnections. The substrates used in this work consisted of a 1.0 μm thick Al layer covered with 1.0–1.5 μm thick CVD silicon dioxide layer. Via holes of 1.5 μm nominal size are formed in the oxide layer by plasma etching. Selective deposition of Ni is achieved by first activating the Al surface in a Pd solution, Ni is then deposited on the activated surface from an aqueous solution using dimethylamineborane or hypophosphite as reducing agents. Pd can be selectively deposited directly on the Al surface without the need of surface activation. Either hypophosphite or hydrazine is used as the reducing agent in the Pd deposition solution. Cobalt can also be selectively deposited to fill the via holes. The filled via holes can have almost perfectly planar surface. Good contact resistance has been obtained by measuring the via chain resistance.