IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1985 · 188 citations · 8 references
EngineeringComputer EngineeringManufacturing EngineeringComputer-aided DesignManufacturing ProcessesSystem-on-chip DesignDefect ModelingDevice ModelingIntegrated Circuit DesignIntegrated Circuit FabricationManufacturing DefectsVery-large-scale Integration LayoutComputer-aided Design For FabricationLayout Parasitics ModelingManufacturing Yield EfficiencyManufacturing Yield ImprovementPoint DefectsRegistration ErrorsYield EnhancementYield Loss Analysis
In this paper, a modeling technique, describing IC manufacturing yield losses in terms of parameters characterizing lithography related point defects and line registration errors, is presented. Optimization of geometrical design rules, evaluation of VLSI IC artwork, and maximization of the wafer yield are discussed as examples illustrating applications and advantages of the proposed modeling technique.
8
Probability, Random Variables, and Stochastic Processes
Irwin Miller · Technometrics · 1966 · 2K citations
Engineering, Mathematics, Physics +14
Integrated circuit yield statistics
C.H. Stapper, F.M. Armstrong, K. Saji · Proceedings of the IEEE · 1983 · 405 citations
Engineering, Electrical Engineering, Manufacturing Engineering +15