50 nm gate electrode patterning using a neutral-beam etching system

Abstract

A 50-nm-width metal-oxide-semiconductor (MOS) gate etching process was established using a recently-developed neutral-beam etching system by optimizing the gas chemistry and the electrode bias condition. In a comparison with poly-Si gate etching using either SF6 or Cl2 gas chemistries, opposite etching characteristics were observed in the pattern profile. Consequently, the use of a mixture of these gases was proposed in order to achieve fine control of the etching profiles. The energy of the neutral beam was increased by applying a 600 kHz rf bias to the bottom electrode. The rf bias was very effective in increasing the etch rate and the anisotropy of the poly-Si gates, with no deterioration of the neutralization efficiency. The oxide leakage current achieved for a MOS capacitor etched by the neutral beam was one order of magnitude lower than that achieved by conventional plasma etching.