IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2000 · 107 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDevice ModelingDevice SimulationIntegrated Circuit DesignPower DissipationShort-channel EffectsChannel Length ScalingCmos Logic CircuitsCmos Logic DesignCmos ScalingScaling Effects In CmosShort-channel Scaling TheoryShort-circuit AnalysisShort-circuit Power
A closed-form expression for short-circuit power dissipation of CMOS gates is presented which takes short-channel effects into consideration. The calculation results show good agreement with the SPICE simulation results over wide range of load capacitance and channel length. The change in the short-circuit power, P/sub S/, caused by the scaling in relation to the charging and discharging power, P/sub D/, is discussed and it is shown that basically power ratio, P/sub S//(P/sub D/+P/sub S/), will not change with scaling if V/sub TH//V/sub DD/ is kept constant. This paper also handles the short-circuit power of series-connected MOSFET structures which appear in NAND and other complex gates.
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