Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits

TLDR

Short‑circuit dissipation in static CMOS inverters varies with load capacitance, as detailed in the discussion. A simple formula for maximum short‑circuit dissipation is derived and applied to CMOS buffer design, including an expression for tapering successive inverters to reduce parasitic power. Equal rise and fall times reduce short‑circuit dissipation to less than 20 % of dynamic, and power‑optimized designs improve speed, power, and area compared to delay‑optimized ones.

Abstract

A simple formula is derived for quick calculation of the maximum short-circuit dissipation of static CMOS circuits. A detailed discussion of this short-circuit dissipation is given based on the behavior of the inverter when loaded with different capacitances. It was found that if each inverter of a string is designed in such a way that the input and output rise and fall times are equal, the short-circuit dissipation will be much less than the dynamic dissipation (<20%). This result has been applied to a practical design of a CMOS driving circuit (buffer), which is commonly built up of a string of inverters. An expression has also been derived for a tapering factor between two successive inverters of such a string to minimize parasitic power dissipation. Finally, it is concluded that optimization in terms of power dissipation leads to a better overall performance (in terms of speed, power, and area) than is possible by minimization of the propagation delay.