Logic BIST Architecture for System-Level Test and Diagnosis

Abstract

This paper describes the logic built-in self-test (BIST) architecture for test and diagnosis of ASIC devices at the system level. The proposed architecture supports the at-speed staggered launch-on-capture clocking scheme and includes novel features to further increase the device's defect coverage, place-and-route ability, ease of debug and diagnosis, and reduce test power consumption. These features include equivalent clock merging for routing considerations, programmable shift modes for overheat considerations, configurable capture modes for yield loss and IR-drop considerations, as well as BIST signature diagnosis, masked-chain diagnosis, and one-chain diagnosis at the system level. Experimental results have successfully demonstrated the feasibility of using the proposed features for system-level test and diagnosis.