Systems-level Test

A "Systems-Level Test" is a formal verification process, belonging to the class of systems engineering validation methods, that evaluates the integrated performance and interoperability of all spacecraft subsystems as a complete functional unit under simulated operational conditions.

90

Publications

2.3K

Citations

408

Authors

149

Institutions

Publications per year

2017–2026

24

Authors

408

  1. MK
    Ming‐Dou Ker

    National Yang Ming Chiao Tung University, Taiwan

    5 publications · 167 citations

    5

    h-index

  2. MS
    M. Sonza Reorda

    Politecnico di Torino, Italy

    3 publications · 91 citations

    3

    h-index

  3. CY
    Cheng-Cheng Yen

    National Yang Ming Chiao Tung University, Taiwan

    3 publications · 90 citations

    3

    h-index

  4. PB
    Paolo Bernardi

    Politecnico di Torino, Italy

    3 publications · 91 citations

    3

    h-index

  5. OF
    Orhan Feyzıog̃lu

    Galatasaray University, Türkiye

    2 publications · 26 citations

    2

    h-index

1–5 of 408

Venues

  1. 2

    h-index

  2. IEEE Transactions on Electron Devices

    2 publications · 77 citations

    2

    h-index

  3. IEEE Design & Test of Computers

    2 publications · 28 citations

    2

    h-index

  4. ACM Transactions on Software Engineering and Methodology

    TOSEM · 2 publications · 61 citations

    2

    h-index

  5. 2

    h-index

1–5