IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1987 · 96 citations · 6 references
EngineeringComputer EngineeringComputer ScienceFault-tolerant ComputingFault-tolerant SystemsTest ConstructionBuilt-in Self-testCombinational Logic DescriptionDesign For TestabilityFault DetectionAutomatic Test Pattern GenerationCombinational Logic DesignFault CoverageFault Coverage AnalysisFault SimulationStuck-at Fault TestingTest GenerationTestability
This paper presents ESPRIT, an automatic test pattern generation (ATPG) system for testing single stuck-at faults in combinational logic. ESPRIT generates test patterns by performing fault simulation on random patterns derived from nonuniformly distributed input signal probabilities. The system computes input signal probabilities that minimize a testability cost function. Using ESPRIT, we have observed orders-of-magnitude reduction in the number of random trials required to obtain a given fault coverage.
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