IEEE Transactions on Computers · 1975 · 179 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringDesign AutomationFault-tolerant ComputingTest ConstructionBuilt-in Self-testDesign For TestabilityDigital Logic DesignLogic SynthesisPattern GenerationAutomatic Test Pattern GenerationCmos Logic CircuitsDigital Logic CircuitsHeuristic AlgorithmsLogic Built-in Self-testPatternsTest GenerationVery-large-scale Integration
A heuristic method for generating large-scale integration (LSI) test patterns is described. In particular, this paper presents a technique for generating statistically random sequences to test complex logic circuits. The algorithms used to obtain a set of tests by means of weighted logic signal variations are included. Several techniques for assigning these weights and for varying them are discussed on the basis of the primary algorithm. Also described is a means of obtaining a minimal number of test patterns. This approach has proved successful in obtaining fault-detecting patterns.
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K.W. Cattermole · Electronics and Power · 1968 · 1.3K citations
Algorithms for Detection of Faults in Logic Circuits
W. G. Bouricius, E.P. Hsieh, G. R. Putzolu et al. · IEEE Transactions on Computers · 1971 · 44 citations