New memory sense amplifier designs in CMOS technology

Abstract

In this paper two-stage sense amplifier designs are proposed which are suitable for current sensing in SRAM and flash memories read operations. The first-stage of these sense amplifiers is characterized by its low power operation and its small area overhead which requires only three transistors in the pitch of a bit line pair for the sensing of the stored data in the selected memory cell. Compact layout designs and simulations in 0.25 /spl mu/m CMOS technology have been carried out to evaluate the efficiency of the proposed schemes.