Characterization of transistor mismatch for statistical CAD of submicron CMOS analog circuits

Abstract

The use of a four-parameter MOS model to characterize drain current mismatch is discussed. Guidelines for the accurate and repeatable measurement of transistor parameter mismatch are presented, along with two extraction methodologies based upon these guidelines. Parameter mismatch measurements made on 430 NMOS and 430 PMOS transistor pairs fabricated in a 0.8-/spl mu/m process are used to predict the drain current mismatch of the same population of transistors. Comparisons are made between the predicted and measured values.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>