A four-level-metal fully planarized interconnect technology for dense high performance logic and SRAM applications

Abstract

The authors describe a four-level-metal (4LM) interconnect technology used to wire high-density, high-performance logic and SRAM chip designs. Process features includes oxide planarization under all metal levels, tungsten studs for contacts and interlevel vias, layered titanium and aluminium-0.5% copper metal lines patterned by reactive ion etch (RIE), and fusible metal links for redundancy applications. Functional 300K circuit ASIC logic test sites (4LM) and 256K SRAMs (3LM) have been fabricated in both 125-mm and 200-mm wafer sizes. Process details are described along with the results of standard electrical tests and reliability stresses.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>