Submicron wiring technology with tungsten and planarization

Abstract

A versatile wiring technology has been developed which is suitable for high-density memory and multilevel logic applications. This fully integrated technology features CVD-tungsten (W) and planarization. Virtual W studs maximise density by reducing contact/via ground rules and by facilitating the use of thick insulators for minimum capacitance. Complementary insulator and W planarization eliminate steps and ease patterning. As a result, circuit performance is enhanced without sacrificing yield or reliability. The chosen materials and process combinations make possible aggressive metal pitch for DRAM, reliable space saving vertical studs for contact/via intensive SRAM, and provide vertical wiring for high-density multilevel logic. Device and reliability results are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>