Electrical Overstress/Electrostatic Discharge Symposium · 2011 · 11 citations · 12 references
EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSimulation-based DesignDesign For TestabilityDevice CharacterizationDevice ModelingDevice SimulationElectrical System TestingSimulation-based ValidationCircuit SimulationFault SimulationReliability SimulationSingle Event Upset ModelingValidation Of Integrated Circuits
A flow and a CAD tool for the simulation of the ESD CDM classification test event in SPICE is described. The methodology consists of deconstructing the CDM test into its relevant components. The modeling and calibration of each component is shown to be essential in the development of a generic simulation approach predicting CDM pass and fail levels. The successful implementation of the flow is demonstrated with a real circuit design example.
12
Self-heating in high performance bipolar transistors fabricated on SOI substrates
Ganci, Hajjar, C. P. Clark et al. · 1992 · 43 citations