A 2nd generation 440 ps SOI 64 b adder

Abstract

Silicon-on-insulator (SOI) technology allows higher performance than bulk technology. However, the floating body effect in SOI devices poses challenges via history effects, bipolar currents, and lower noise margins on dynamic circuits. This 64 b adder is used to compute the effective address in a PowerPC/sup TM/ processor. Particular emphasis is on design issues, advantages resulting from unique SOI device structures, and the techniques for controlling floating body effect in partially-depleted devices. Adder performance comparison is shown for bulk CMOS, first-generation SOI CMOS, and second generation SOI CMOS.