S.N. Storino - Concepedia

Author

S.N. Storino

Also Known As

S. Storino, S.N. Storino, Salvatore N. Storino

Publications

151

Citations

H-Index

Concepts

All Affiliations

S.N. Storino is an author at IBM (United States) specializing in computer engineering, engineering, and computer architecture.

#	Concept	H-Index	Publications	Citations
1	Engineering	6	6	141
2	Computer Engineering	6	6	141
3	Computer Architecture	6	6	141
4	Electrical Engineering	5	5	117
5	Computer Science	1	1	24

S.N. Storino

Publications

141

Citations

H-Index

Page 1

	Year	Citations
A 0.2-μm, 1.8-V, SOI, 550-MHZ, 64-b PowerPC microprocessor with copper interconnects A.G. Aipperspach, D.H. Allen, D. Cox, IEEE Journal of Solid-State Circuits Low-power ElectronicsSystem On ChipElectrical Engineering64-B Powerpc MicroprocessorEngineering	1999	55
A 4R2W register file for a 2.3GHz wire-speed POWER&#x2122; processor with double-pumped write operation Gary S. Ditlow, Robert K. Montoye, S.N. Storino, EngineeringVlsi DesignComputer ArchitectureMulti-channel Memory ArchitectureHardware Security	2011	28
A commercial multithreaded RISC processor S.N. Storino, A. Aipperspach, John M. Borkenhagen, Hardware SecurityProcessor LogicEngineeringProcessor Architecture RegistersRisc-v	2002	24
A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology D. Stasiak, F. Mounes-Toussi, S.N. Storino IEEE Journal of Solid-State Circuits Electrical EngineeringSoi Technology64-Bit AdderVlsi DesignEngineering	2001	12
A 2nd generation 440 ps SOI 64 b adder D. Stasiak, J. Tran, F. Mounes-Toussl, System On ChipElectrical EngineeringEngineeringVlsi DesignAdvanced Packaging (Semiconductors)	2002	11
A double-precision multiplier with fine-grained clock-gating support for a first-generation CELL processor J.B. Kuang, T.C. Buchholtz, S.M. Dance, EngineeringVlsi DesignRadio FrequencyComputer ArchitectureProcessor Architecture	2005	11

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