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Three micron CMOS technology for custom high reliability and radiation-hardened integrated circuits
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1983
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EngineeringVlsi DesignMicron Cmos ProcessComputer ArchitectureIntegrated CircuitsSilicon On InsulatorHardware SecurityAdvanced Packaging (Semiconductors)Cmos TechnologyMicron Cmos TechnologyElectronic PackagingElectrical EngineeringHardware ReliabilityRadiation-hard DesignSingle Level PolysiliconComputer EngineeringSemiconductor Device FabricationCustom High ReliabilityMicroelectronicsDevice ReliabilityMicrofabricationRadiation-hardened Integrated CircuitsCircuit ReliabilityNew Radiation
A new radiation hardened three micron CMOS process has been developed. It uses a guardbanded P-well with single level polysilicon and single level metal. Plasma processing is used for etching the critical dimension levels of polysilicon, contact window and metal. To date, fifteen designs have been fabricated using the technology. These include CMOS equivalents of the Intel 8085 8-bit microprocessor family, two custom encryption chips of about 19,000 transistors each and custom logic designs using Sandia's standard cell family. Performance of the devices has exceeded all specifications.