2004 · 64 citations · 7 references
EngineeringComputer EngineeringComputer ScienceFault ToleranceFault-tolerant ComputingField-programmable Gate ArraysConfigurable Logic BlocksConfiguration MemoryField-programmable Gate Array ArchitectureFpga ArchitectureHardware Fault ToleranceMemory Subsystem DesignConfiguration Memory Power ReductionFault-tolerant ArchitectureLeakage-aware Memory DesignMemory Fault ToleranceRadiation-hardened Configuration MemorySoft Error Mitigation In Configuration MemorySoft ErrorsStatic Random-access Memory Design
Soft errors that change configuration bits of an SRAM based FPGA modify the functionality of the design. The proliferation of FPGA devices in various critical applications makes it important to increase their immunity to soft errors. In this work, we propose the use of an asymmetric SRAM (ASRAM) structure that is optimized for soft error immunity and leakage when storing a preferred value. The key to our approach is the observation that the configuration bitstream is composed of 87% of zeros across different designs. Consequently, the use of ASRAM cell optimized for storing a zero (ASRAM-0) reduces the failure in time by 25% as compared to the original design. We also present an optimization that increases the number of zeros in the bitstream while preserving the functionality.
7
Leakage power analysis of a 90nm FPGA
Tim Tuan, B. Lai · 2004 · 165 citations
Engineering, Computer Engineering, Electrical Engineering +17
Active leakage power optimization for FPGAs
Jason H. Anderson, Farid N. Najm, Tim Tuan · 2004 · 103 citations
Engineering, Computer Engineering, Electrical Engineering +17