Leakage power analysis of a 90nm FPGA

Abstract

Reconfigurable architectures, including FPGAs, are promising solutions for managing increasing design complexity while achieving both performance and flexibility. To support reconfiguration, FPGAs use more transistors per function than fixed-logic solutions, resulting in higher leakage power consumption. Consequently, FPGAs are generally not found in mobile applications. In this work, we analyze the leakage power of a low-cost, 90 nm FPGA using detailed device-level simulations. The simulation methodology accounts for design-dependent variations and provides detailed leakage power breakdowns. The analysis quantifies the leakage power challenge in FPGAs, and identifies promising approaches for FPGA leakage power reduction.