Memory Fault Tolerance
Memory Fault Tolerance is a design methodology in computer architecture that ensures reliable data storage and retrieval despite hardware defects or transient errors in memory systems by incorporating redundancy, error-correcting codes, or fault-detecting mechanisms to maintain system integrity and continuity of operation.
494
Publications
21.7K
Citations
1.2K
Authors
349
Institutions
Publications per year
2017–2026
65
Parents
494
Bianca Schroeder, Eduardo Pinheiro, Wolf-Dietrich Weber · 2009 · 556 citations
Bit error rate in NAND Flash memories
Neal Mielke, Todd A. Marquart, Ning Wu et al. · 2008 · 358 citations
Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis
Yu Cai, Erich F. Haratsch, Onur Mutlu et al. · 2012 · 321 citations
1–5 of 494
1.2K
Advanced Micro Devices (United States), United States
16 publications · 1.1K citations
15
h-index
12
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10
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10
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10
h-index
1–5 of 1.2K
349
IBM (United States)
Armonk, United States
17 h-index
44 publications
1.8K citations
Intel (United States)
Santa Clara, United States
16 h-index
44 publications
6.1K citations
Carnegie Mellon University
Pittsburgh, United States
14 h-index
47 publications
6.4K citations
Advanced Micro Devices (United States)
Sunnyvale, United States
14 h-index
27 publications
1.3K citations
Georgia Institute of Technology
Atlanta, United States
13 h-index
23 publications
2.2K citations
University of Pittsburgh
Pittsburgh, United States
12 h-index
46 publications
786 citations
University of Illinois Urbana-Champaign
Urbana, United States
12 h-index
29 publications
829 citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
12 h-index
31 publications
1.7K citations
1–8 of 349
47 publications · 1.5K citations
24
h-index
17 publications · 768 citations
16
h-index
20 publications · 887 citations
15
h-index
11 publications · 583 citations
11
h-index
9 publications · 326 citations
9
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1–5