Memory Fault Tolerance

Memory Fault Tolerance is a design methodology in computer architecture that ensures reliable data storage and retrieval despite hardware defects or transient errors in memory systems by incorporating redundancy, error-correcting codes, or fault-detecting mechanisms to maintain system integrity and continuity of operation.

494

Publications

21.7K

Citations

1.2K

Authors

349

Institutions

Publications per year

2017–2026

65

Authors

1.2K

  1. VS
    Vilas Sridharan

    Advanced Micro Devices (United States), United States

    16 publications · 1.1K citations

    15

    h-index

  2. OM
    Onur Mutlu

    Carnegie Mellon University, United States

    13 publications · 1.5K citations

    12

    h-index

  3. RM
    Rami Melhem

    University of Pittsburgh, United States

    10 publications · 186 citations

    10

    h-index

  4. JL
    Jin-Fu Li

    National Central University, Taiwan

    10 publications · 273 citations

    10

    h-index

  5. CW
    Cheng‐Wen Wu

    National Tsing Hua University, Taiwan

    10 publications · 518 citations

    10

    h-index

1–5 of 1.2K

Venues

  1. IEEE Transactions on Computers

    47 publications · 1.5K citations

    24

    h-index

  2. IEEE Transactions on Nuclear Science

    17 publications · 768 citations

    16

    h-index

  3. 15

    h-index

  4. IEEE Journal of Solid-State Circuits

    11 publications · 583 citations

    11

    h-index

  5. 9

    h-index

1–5