Consideration of age degradation in the RF performance of CMOS radio chips for high volume manufacturing

Abstract

The age reliability of the RF performance of CMOS radio chips must be validated prior to high volume manufacturing. In this paper, we show the results of age simulations on some RF subblock designs used in our 802.11 a/b/g radio chip transceiver for our WLAN card. Transistor age models, based on HCI and NBTI age degradation mechanisms, were derived from stress measurements made on a variety of NMOS and PMOS transistors. They were used in full circuit level age simulations on a driver amplifier and a mixer design, presented here, using Cadence's RelXpert simulator, which allows for age modeling from the single transistor level up to the entire TX and RX chain hierarchies.