1985 · 17 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDynamic Power ReductionLow-power Digital Circuit DesignMemory DevicesMemory Subsystem DesignPower ManagementDynamic Power DissipationEnergy-efficient Memory DesignLow-power Memory ArchitectureLow-power Memory CircuitsMemory Circuit DesignMemory Power ManagementNon-volatile Memory DesignPower-efficient Memory Design
A 45ns 256K (32K×8b) CMOS SRAM with a 200mW at 10MHz active power dissipation will be described. The RAM utilizes variable impedance data-line loads, pulsed word lines and latched output buffers. A polycide vss-line is used in a 95μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> memory cell.
3
O. Minato, T. Masuhara, Takeshi Sasaki et al. · 1984 · 35 citations
Engineering, Computer Engineering, Electrical Engineering +17
Satoshi Konishi, J. Matsunaga, T. Ohtani et al. · 1982 · 29 citations
Engineering, Computer Engineering, Electrical Engineering +16
S. Meguro, Sho Ikeda, Kensaku Nagasawa et al. · 1984 · 13 citations
Engineering, Electrical Engineering, Electronic Materials +14