Photomask Layout
Photomask Layout is a specialized geometric design representing the pattern of an integrated circuit layer, serving as a photolithographic template in semiconductor manufacturing to selectively transmit or block light during wafer fabrication.
22
Publications
569
Citations
79
Authors
25
Institutions
Publications per year
2017–2026
2
Variants
Mask Layout
Parents
22
Robust level-set-based inverse lithography
Yijiang Shen, Ningning Jia, Ngai Wong et al. · Optics Express · 2011 · 75 citations · Full text
A new IGBT with a monolithic over-current protection circuit
Y. Seki, Yoshihisa Harada, Noriyuki Iwamuro et al. · 2002 · 35 citations
1–5 of 22
79
National Institute of Standards and Technology, United States
1 publications · 23 citations
1
h-index
1
h-index
1
h-index
National Institute of Standards and Technology, United States
1 publications · 23 citations
1
h-index
1
h-index
1–5 of 79
25
National Institute of Standards and Technology
Gaithersburg, United States
2 h-index
6 publications
129 citations
HTC (Taiwan)
Banqiao District, Taiwan
1 h-index
1 publications
37 citations

National Yang Ming Chiao Tung University
Hsinchu, Taiwan
1 h-index
1 publications
11 citations
University of California, Los Angeles
Los Angeles, United States
1 h-index
3 publications
66 citations

Fu Jen Catholic University
Taipei, Taiwan
1 h-index
1 publications
37 citations
MIT Lincoln Laboratory
Lexington, United States
1 h-index
1 publications
14 citations
IBM Research - Almaden
San Jose, United States
1 h-index
6 publications
168 citations
University of California, Berkeley
Berkeley, United States
1 h-index
2 publications
44 citations
1–8 of 25
5 publications · 160 citations
5
h-index
1 publications · 26 citations
1
h-index
1 publications · 10 citations
1
h-index
1 publications · 14 citations
1
h-index
1 publications · 37 citations
1
h-index
1–5